Surface Charge Density of Unpassivated and Passivated Metal-Catalyzed Silicon Nanowires

Kang-Ill Seo, Shashank Sharma, Amir A. Yasseri, +2

Electrochemical and Solid-State Letters

EngineeringSilicon On InsulatorCharge TransportChemical EngineeringMetal-catalyzed Nanowires +14

Chemical states and electronic structure of a HfO2∕Ge(001) interface

Kang-Ill Seo, Paul C. McIntyre, Shiyu Sun, +3

Applied Physics Letters

Valence Band AlignmentEngineeringCrystalline DefectsChemical BondSurface Science +8

Formation of an interfacial Zr-silicate layer between ZrO2 and Si through <i>in situ</i> vacuum annealing

Kang-Ill Seo, Paul C. McIntyre, Hyoungsub Kim, +1

Applied Physics Letters

Materials ScienceMaterial AnalysisEngineeringNanomaterialsNanotechnology +11

Chemical states and electrical properties of a high-k metal oxide/silicon interface with oxygen-gettering titanium-metal-overlayer

Kang-Ill Seo, Dong-Ick Lee, P. Pianetta, +3

Applied Physics Letters

EngineeringOxidation ResistanceSio2 IlIntegrated CircuitsSilicon On Insulator +16

Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices

Kwan-Yong Lim, Hyun‐Jung Lee, Choongryul Ryu, +21

Materials EngineeringElectrical EngineeringEngineeringNanoelectronicsStress-induced Leakage Current +11

A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

Dong-il Bae, Geum-Jong Bae, Krishna K. Bhuwalka, +23

Electrical EngineeringLogic ApplicationsEngineeringVlsi DesignSige Device +11

Random Telegraph Noise in n-type and p-type silicon nanowire transistors

Seungwon Yang, Kyoung Hwan Yeo, Dong‐Won Kim, +5

Electrical EngineeringEngineeringPhysicsRandom Telegraph NoiseNanoelectronics +11

Improvement in high-k (HfO/sub 2//SiO/sub 2/) reliability by incorporation of fluorine

Kang-Ill Seo, R. Sreenivasan, Paul C. McIntyre, +1

Materials ScienceMaterials EngineeringElectrical EngineeringSi-h BondsEngineering +12

Backside Power Distribution for Nanosheet Technologies Beyond 2nm

Ruilong Xie, Wonhyuk Hong, Chen Zhang, +50

Interface Layers for High-k/Ge Gate Stacks: Are They Necessary?

Paul C. McIntyre, David Chi, Chi On Chui, +7

ECS Transactions

Electrical EngineeringSemiconductor DeviceEngineeringPhysicsGe Substrate +11