Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices

Abstract

High-k/metal gate (HKMG) compatible high performance Source/Drain (S/D) stress-memorization-technology (SMT) is presented. Channel stress generated by SMT can be simulated by using mask-edge dislocation model, which is consistent with the measured actual channel stress. Extremely deep pre-amorphization-implant (PAI) for SMT creates multiple mask-edge dislocations under S/D region, which enhances short-channel mobility by 40~60%. Finally, more than 10% short channel drive current gain is achieved with additional S/D extension optimization.