InAs FinFETs With H_finnm Fabricated Using a Top–Down Etch Process

Abstract

We report the first demonstration of InAs FinFETs with fin width <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textrm {W}_{{\mathrm{fin}}}$ </tex-math></inline-formula> in the range 25–35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textrm {H}_{{\mathrm{fin}}}=20$ </tex-math></inline-formula> nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textrm {L}_{{{\textrm {g}}}}=1~\mu \text{m}$ </tex-math></inline-formula> , peak transconductance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textrm {g}_{{{\textrm {m},{\mathrm{ peak}}}}}=1430~\mu \text{S}/\mu \text{m}$ </tex-math></inline-formula> is measured at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textrm {V}_{{\textrm {d}}}=0.5$ </tex-math></inline-formula> V demonstrating that electron transport in InAs fins can match planar devices.