IEEE Journal of Solid-State Circuits · 2013 · 81 citations · 11 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsIntegrated Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationNoise In Analog CircuitsTiming AnalysisTiming ModelingClock Jitter ModelingInjection TimingJitterPhase NoisePhase Noise AnalysisPhase Noise CompensationPower ConsumptionRadio-frequency Integrated Circuit Design
A 2.4-GHz subharmonically injection-locked PLL (SILPLL) with injection timing calibration is realized. The injection timing issues has been clearly described and modeled mathematically. An injection timing calibration technique is presented to ensure the best phase noise performance. This work is fabricated in 0.18-μm process with 12.6-mW power consumption. The measured phase noises at 1 MHz offset before and after injection are -114 and -129 dBc/Hz, respectively. The measured rms jitter integrated from 1 kHz to 40 MHz before and after injection are 317 and 145 fs, respectively.
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Belal M. Helal, Matthew Z. Straayer, Gu-Yeon Wei et al. · IEEE Journal of Solid-State Circuits · 2008 · 116 citations
Engineering, Computer Engineering, Electrical Engineering +17