Belal M. Helal

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance

Belal M. Helal, Matthew Z. Straayer, Gu-Yeon Wei et al. · IEEE Journal of Solid-State Circuits · 2008 · 116 citations

Engineering, Clock Recovery, Mdll Output +13

A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop

Belal M. Helal, Chun-Ming Hsu, Kerwin Johnson et al. · IEEE Journal of Solid-State Circuits · 2009 · 109 citations · Full text

Engineering, Analog-to-digital Converter, High-frequency Device +9

8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET

Parmanand Mishra, A. Tan, Belal M. Helal et al. · 2021 · 73 citations

Engineering, Forward Error Correction, Analog-to-digital Converter +12

3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS

K. Gopalakrishnan, Alan Ren, A. Tan et al. · 2016 · 61 citations

Pam-4 Ethernet Transceiver, Wireless Communications, Engineering +10

A Low Jitter 1.6 GHz Multiplying DLL Utilizing a Scrambling Time-to-Digital Converter and Digital Correlation

Belal M. Helal, Matthew Z. Straayer, Gu-Yeon Wei et al. · 2007 · 54 citations

Low Jitter 1.6, Engineering, Clock Recovery +11