Performance limits of planar and multi-layer integrated inductors

Abstract

The performance of integrated inductors is quantified, with respect to geometrical parameters and silicon process characteristics. A custom EDA tool is employed for modeling and simulating an assortment of inductor topologies under various process schemes. The aim is to outline inductor performance limits, mainly in terms of inductance, quality factor and resonant frequency. Also, guidelines are provided for their optimal physical design and for process enhancements that may benefit their performance in RF ICs.