Spiral inductors and transmission lines in silicon technology using copper-damascene interconnects and low-loss substrates

TLDR

The fabrication process is compatible with standard silicon device fabrication concepts. Spiral inductors and various transmission lines were fabricated using copper damascene interconnects on high‑resistivity silicon or sapphire substrates. The fabricated 1.4‑nH inductors achieved Q factors of 30 at 5.2 GHz and 40 at 5.8 GHz on HRS and sapphire, while 80‑nH inductors reached Q ≈ 13; transmission‑line losses were about 4 dB/cm at 10 GHz, demonstrating high‑Q lumped elements in the 1–10 GHz range and low‑loss distributed elements above 10 GHz.

Abstract

Spiral inductors and different types of transmission lines are fabricated by using copper (Cu)-damascene interconnects and high-resistivity silicon (HRS) or sapphire substrates. The fabrication process is compatible with the concepts of silicon device fabrication. Spiral inductors with 1.4-nH inductance have quality factors (Q) of 30 at 5.2 GHz and 40 at 5.8 GHz for the HRS and the sapphire substrates, respectively. 80-nH inductors have Q's as high as 13. The transmission-line losses are near 4 dB/cm at 10 GHz for microstrips, inverted microstrips, and coplanar lines, which are sufficiently small for maximum line lengths within typical silicon-chip areas. This paper shows that inductors with high Q's for lumped-element designs in the 1-10-GHz range and transmission lines with low losses for distributed-element designs beyond 10 GHz can be made available with the proposed adjustments to commercial silicon technology.