Warpage measurement of large area multitilted silicon substrates at various processing conditions

Abstract

In order to find a low-cost solution for the future MCM-D packaging, a multitiling approach through the incorporation of several tiles on a large carrier substrate was studied. The multitiling format provides simultaneous processing of several small silicon wafers on a carrier glass with a coefficient of thermal expansion (CTE) comparable to that of silicon. The wafers (tiles) are attached to the carrier glass (pallet) using a low modulus adhesive that can be released at an elevated temperature (/spl sim/450/spl deg/C). The objective of this study is to develop materials and processes for a 12-in/spl times/12-in (300-mm/spl times/300-mm) large area substrate that can be scalable up to a 600-mm/spl times/600-mm format. The fabrication process begins with a carrier CTE matched Borofloat glass on which silicon wafers are attached using a low modulus adhesive. This composite structure is exposed to high temperature thin-film processes that are required for the MCM-D manufacturing. The warpage of these structures is a critical factor that determines the processability of the thin films in a manufacturing environment. Specimen warpage was obtained using the shadow moire technique. Warpage measurement was performed (i) on as-received glasses, (ii) glasses after polishing, and (iii) pallet assembly after tiling was completed. Although polishing reduced the overall warpage of the as-received pallets, the warpage of the tile and pallet assembly was increased after the adhesive was cured at 150/spl deg/C. This paper discusses the warpage issues associated with various stages of processing of the proposed large area MCM-D structures.