Domain wall motion based magnetic adder

Abstract

Presented is the first design of a multi-bit magnetic adder (MA) based on domain wall (DW) motion. All the input and output signals are stored in non-volatile DW shift registers instead of CMOS registers. One can turn off safely the logic circuits without data backup and power them on instantly. This new function promises to overcome completely the rising standby power issue. Moreover, the direct integration of the memory cell in logic circuits reduces greatly the dynamic power dedicated to data moving between logic and memory. An 8-bit MA has been successfully simulated based on a 65 nm node.