A high-speed low-power Hi-CMOS 4K static RAM

O. Minato, T. Masuhara, Takeshi Sasaki, Yoshio Sakai, Mitsuo Kubo, K. Uchibori, T. Yasui

IEEE Transactions on Electron Devices · 1979 · 16 citations · 3 references

Concepts

Abstract

A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realized using low-power-oriented circuit design and high-performance CMOS technology utilizing 3-µm gate length. The fabricated 4K static RAM has an address access time of 43 ns and a power dissipation of 80 mW.

References

3