Realization of a stackable package using chip in polymer technology

Abstract

The coming generations of portable products require significant improvement of the packaging technologies, mainly due to increasing signal frequencies and the demand for higher density of functions. State of the art are organic substrates with micro-via build-up layers, equipped on both sides with discrete passive and active components. The space requirement of active chips can be already reduced to a minimum by implementing CSPs (chip size packages) or flip chips. A further miniaturization however requires a 3-dimensional integration of active and passive components. Additionally the signal frequencies will increase to several GHz in high speed digital applications. In order to maintain signal integrity, much shorter and impedance-matched interconnects between chips and passive components are required. In this paper a new approach will be described which allows both extreme dense 3-dimensional integration and very short interconnects. This approach, called "Chip in Polymer" is based on the integration of thin components into build-up layers of printed circuit boards.