Design and fabrication of a reliability test chip for 3D-TSV

Abstract

A test chip has been designed and fabricated to validate the performance, yield and reliability of 3D chip stacks using Through Silicon Vias (TSVs). The test chip contains test structures designed to measure the electromigration performance of TSVs and microbump, thermal performance, stress in the chip as a result of thinning and die stacking, and corrosion related to moisture ingress. The structures are designed to facilitate failure analysis, allowing fault isolation to be done by electrical characterization as far as possible.