Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors

Concepts

EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignDevice ModelingIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsCurrent-voltage RelationsFin Field-effect Transistors

Abstract

We proposed a new bulk FinFET that has a p + /n + poly-Si gate consists of p + region near the source and n + region near the drain and analyzed current-voltage characteristics and electric field profiles of 50-nm devices by changing the n + poly-Si gate length (L s ). For given gate length (L g les50 nm) and fin body width (W fin les30 nm), L s was designed to satisfy the I off requirement (i.e., 1 fA) of DRAM cell. Optimum L s /L g of 30-nm device was ~0.4 at a W fin of 10 nm and ~0.2 at a W fin of 15 nm

References

Dual material gate field effect transistor (DMGFET)

Wei Long, Ken K. Chin · 2002 · 98 citations

Engineering, Electrical Engineering, Materials Science +14

An accurate model of subbreakdown due to band-to-band tunneling and some applications

Tetsuo Endoh, R. Shirota, M. Momodomi et al. · IEEE Transactions on Electron Devices · 1990 · 59 citations

Engineering, Electrical Engineering, Microelectronics +16

Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

Sung-Wook Park, Sung-Joo Hong, Jin Woong Kim et al. · 2006 · 47 citations

Engineering, Electrical Engineering, Microelectronics +13

S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

Young‐Wook Kim, H.J. Oh, D. S. Woo et al. · 2005 · 38 citations

Engineering, Computer Engineering, Electrical Engineering +17

GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices

Thomas Hoffmann, Abhisek Dixit, K. De Meyer et al. · 2005 · 34 citations

Engineering, Electrical Engineering, Materials Science +17