Redundancies and don't cares in sequential logic synthesis

MIS: A Multiple-Level Logic Optimization System

Robert K. Brayton, Richard Rudell, Alberto Sangiovanni‐Vincentelli et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1987 · 1.2K citations

Engineering, Computer Engineering, Computer Science +16

An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits

 Goel · IEEE Transactions on Computers · 1981 · 1.1K citations

Engineering, Computer Engineering, Computer Science +12

Diagnosis of Automata Failures: A Calculus and a Method

J. P. Roth · IBM Journal of Research and Development · 1966 · 898 citations

Computing, Computer Engineering, Computer Science +10

Minimizing the Number of States in Incompletely Specified Sequential Switching Functions

M. C. Paull, S.H. Unger · IEEE Transactions on Electronic Computers · 1959 · 324 citations

Computing, Computer Science, Mathematics +8

MUSTANG: state assignment of finite state machines targeting multilevel logic implementations

Srinivas Devadas, Hi-Keung Ma, A. Richard Newton et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1988 · 283 citations

Engineering, Computer Engineering, Computer Science +16