Sequential Logic Synthesis

Sequential Logic Synthesis is a formal method within logic synthesis that optimizes and constructs sequential circuits by transforming high-level behavioral specifications into efficient hardware implementations while preserving temporal behavior and minimizing area, delay, or power over clocked systems with memory elements.

218

Publications

11.4K

Citations

400

Authors

163

Institutions

Publications per year

2017–2026

10

Authors

400

  1. RK
    Robert K. Brayton

    University of California, Berkeley, United States

    24 publications · 1.4K citations

    16

    h-index

  2. SD
    Srinivas Devadas

    Massachusetts Institute of Technology, United States

    20 publications · 998 citations

    16

    h-index

  3. AS
    Alberto Sangiovanni‐Vincentelli

    University of California, Berkeley, United States

    14 publications · 1.1K citations

    13

    h-index

  4. AR
    A. Richard Newton

    University of California, Berkeley, United States

    13 publications · 531 citations

    12

    h-index

  5. AM
    Alan Mishchenko

    University of California, Berkeley, United States

    10 publications · 318 citations

    10

    h-index

1–5 of 400

Venues

  1. 18

    h-index

  2. IEEE Transactions on Computers

    19 publications · 837 citations

    15

    h-index

  3. IEEE Transactions on Electronic Computers

    5 publications · 176 citations

    5

    h-index

  4. Electronics Letters

    3 publications · 41 citations

    3

    h-index

  5. Journal of Electronic Testing

    JETTA · 2 publications · 47 citations

    3

    h-index

1–5