Sequential Logic Synthesis
Sequential Logic Synthesis is a formal method within logic synthesis that optimizes and constructs sequential circuits by transforming high-level behavioral specifications into efficient hardware implementations while preserving temporal behavior and minimizing area, delay, or power over clocked systems with memory elements.
218
Publications
11.4K
Citations
400
Authors
163
Institutions
Publications per year
2017–2026
10
Parents
218
SIS : A System for Sequential Circuit Synthesis
Ellen Sentovich · 1992 · 1.9K citations
Sequential circuit design using synthesis and optimization
Ellen Sentovich, K.J. Singh, Cho W. Moon et al. · 2003 · 615 citations
1–5 of 218
400
16
h-index
16
h-index
University of California, Berkeley, United States
14 publications · 1.1K citations
13
h-index
12
h-index
10
h-index
1–5 of 400
163
University of California, Berkeley
Berkeley, United States
24 h-index
98 publications
7K citations
Massachusetts Institute of Technology
Cambridge, United States
15 h-index
31 publications
2K citations
AT&T (United States)
Bedminster, United States
13 h-index
22 publications
2.1K citations
Nokia (United States)
Coppell, United States
8 h-index
15 publications
1.6K citations
Princeton University
Princeton, United States
8 h-index
12 publications
343 citations
Stanford University
Stanford, United States
7 h-index
11 publications
358 citations
Synopsys (United States)
Mountain View, United States
7 h-index
7 publications
238 citations
IBM (United States)
Armonk, United States
6 h-index
7 publications
250 citations
1–8 of 163
25 publications · 1.2K citations
18
h-index
19 publications · 837 citations
15
h-index
5 publications · 176 citations
5
h-index
3 publications · 41 citations
3
h-index
JETTA · 2 publications · 47 citations
3
h-index
1–5