IEEE Journal of Solid-State Circuits · 1994 · 27 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryComputer ArchitectureMicroelectronicsClock Distribution NetworksClock ManagementCmos Circuit DesignDelay ModelingTiming AnalysisTiming ModelingClock Buffer DesignClock Buffer SizingFlip-flop DesignFlip-flopsLimitsNon-ideal SolutionsTimingTiming Violations
Clocked digital circuits are sensitive to changes of the input signals close to the clock transitions. Non ideal properties of the clock transition, such as slope, make timing requirements more complicated. Here we present methods, quantitative limits and clock buffer requirements by studying clock slope impact on TSPC circuits. The investigation is based on SPICE simulations of edge-triggered D flip-flops and latches, implemented in the TSPC technique. The simulation results were also verified by measurements on 2-/spl mu/m CMOS prescalers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
2
High-speed CMOS circuit technique
Jiren Yuan, C. Svensson · IEEE Journal of Solid-State Circuits · 1989 · 792 citations
Engineering, Computer Engineering, Electrical Engineering +16