Clock Buffer Sizing is a design optimization technique in clock distribution networks that determines the optimal sizes of buffer elements to minimize delay, skew, and power consumption while maintaining signal integrity.
23
Publications
712
Citations
44
Authors
16
Institutions
Publications per year
2017–2026
0
Parents
Publications
23
1–5 of 23
Authors
44
- JH
5
h-index
- GV
4
h-index
- PL
3
h-index
- ZF
3
h-index
- XZ
2
h-index
1–5 of 44
Institutions
16
Texas A&M University
College Station, United States
5 h-index
16 publications
421 citations
Intel (United States)
Santa Clara, United States
3 h-index
3 publications
127 citations
University of California, Santa Cruz
Santa Cruz, United States
3 h-index
5 publications
218 citations
Linköping University
Linköping, Sweden
2 h-index
3 publications
127 citations
Georgia Institute of Technology
Atlanta, United States
2 h-index
6 publications
63 citations
University of Utah
Salt Lake City, United States
1 h-index
1 publications
33 citations
Kyoto University
Kyoto, Japan
1 h-index
3 publications
99 citations
University of California, Santa Barbara
Santa Barbara, United States
1 h-index
2 publications
78 citations
1–8 of 16
Venues
- Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design
ICCAD · 3 publications · 76 citations
3
h-index
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2 publications · 54 citations
2
h-index
- IEEE Journal of Solid-State Circuits
2 publications · 100 citations
2
h-index
- Proceedings - ACM IEEE Design Automation Conference
1 publications · 14 citations
1
h-index
- IEEE Transactions on Circuits and Systems I Regular Papers
1 publications · 26 citations
1
h-index
1–5