IEEE Journal of Solid-State Circuits · 1991 · 25 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignDigital Integrated Circuit DesignDigital Logic DesignDynamic Power ReductionIntegrated Circuit DesignLow-power Digital Circuit DesignCarry-lookahead LogicDynamic Logic CircuitsExperimental CharacterizationGate Delay ModelingLogic Gate DelayLogic Gate ImplementationLow-power AddersLow-power Logic Design
Dynamic capacitively coupled domino logic (CCDL) has been proposed as a practical means of implementing low-power and high-speed complex gates. The CCDL gate delay characteristics obtained from an analytical model and from test circuits implemented in a 1- mu m GaAs E/D process are presented. In addition, the feasibility of using CCDL gates to implement practical circuits is demonstrated by the experimental characterization of a 4-b carry-lookahead adder. The adder has a critical delay of 1.1 ns and a power dissipation of 96 mW. A comparison of the dynamic CCDL adder with conventional static designs indicates the advantages of dynamic CCDL gates in reducing power dissipation and increasing speed, making such gates suitable for VLSI implementations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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