Fast cycle RAM (FCRAM); a 20-ns random row access, pipe-lined operating DRAM

Abstract

We propose an ultra-high speed 64-Mbit DRAM, with a random address access time (tRAC) of 26 ns and an address cycle time (tRC) of 20 ns. This memory was built on fundamental changes in the operating concept of DRAMs. The key technologies are described below. (1) Non-address multiplex: this enables minimization of timing lag between the row side and the column side circuitry by adding a timing generator to the chip. This is unlike usual DRAMs in which timings are controlled externally by a CAS clock. The activated block size can be much smaller than usual. Sensing and restore functions are performed by separate circuits, allowing for a minimum delay in the data path. (2) Pipelined operation in RAS circuitry: the DRAM core automatically goes into a reset state after sense/restore operation. After sending data to the output stage, the next row or word line can be driven without any time lag, while the previous data is in the output stage. As a result, the next address can be applied in 20 ns, even for the same bank. Data I/O of this RAM is comprised of a 64-bit parallel port, resulting in 3.2 Gb/s bandwidth even in the random address access mode.