Selecting High-Quality Delay Tests for Manufacturing Test and Debug

Abstract

The process of debugging timing failures requires the selection of a small set of high-quality tests which can excite critical paths and cause a circuit to fail at as low a frequency as possible. Since the primary source of such vectors are functional vectors which can run into millions of cycles, a cost-effective methodology for selecting high quality delay tests should not require an excessive computational effort and should guarantee reasonable accuracy. We propose two metrics for estimating the delay under a given test to aid in ranking tests in order of their ability to excite critical delays. The first metric is path-based, i.e., it estimates delays of excited paths, and associates the worst-case delay over all the excited paths with the test. The second metric is cone-based, i.e., it estimates the worst-case delay for the logic cone of every output without considering paths explicitly, and associates the largest delay over all the cones with the test. For each of these two metrics, we evaluate the correlation between the metric and the delay computed by circuit simulation. Results on combinational benchmark circuits demonstrate that the metrics achieve reasonable accuracy in test selection at a significantly lower computation time than circuit simulation