Suriyaprakash Natarajan

Author

Intel (United States)ORCID

Also Known As

Natarajan, Suriyaprakash, Suriyaprakash Natarajan

Publications

391

Citations

H-Index

Concepts

All Affiliations

Intel (United States)The University of Texas at Dallas Georgia Institute of Technology

About

Suriyaprakash Natarajan is an author at Intel (United States) specializing in engineering, computer engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	8	8	273
2	Computer Engineering	7	7	257
3	Applied Physics	2	2	86
4	Computer Science	2	2	95
5	Data Science	1	1	16

Suriyaprakash Natarajan

Publications

284

Citations

H-Index

Page 1

	Year	Citations
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators Shamik Kundu, Suvadeep Banerjee, Arnab Raha, IEEE Transactions on Very Large Scale Integration (VLSI) Systems EngineeringMachine LearningSuch AcceleratorsHardware AlgorithmComputer Architecture	2021	81
Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays Ashwin Chintaluri, Helia Naeimi, Suriyaprakash Natarajan, IEEE Journal on Emerging and Selected Topics in Circuits and Systems Non-volatile MemoryEngineeringFault ModelsEmerging Memory TechnologyMagnetic Resonance	2016	56
Case Study on Speed Failure Causes in a Microprocessor Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, IEEE Design & Test of Computers EngineeringVlsi DesignComputer ArchitecturePerformance IssueHardware Security	2008	35
A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays Ashwin Chintaluri, Abhinav Parihar, Suriyaprakash Natarajan, Non-volatile MemoryModel StudyEngineeringFault ModelsEmerging Memory Technology	2015	30
The Region-Exhaustive Fault Model Abhijit Jas, Suriyaprakash Natarajan, Srinivas Patil EngineeringFault ModelsHardware SecurityReliability EngineeringFault Analysis	2007	23
Scalable and efficient analog parametric fault identification Mustafa Berke Yelten, Suriyaprakash Natarajan, Bin Xue, International Conference on Computer Aided Design EngineeringVerificationComputer ArchitectureCritical Parametric FaultsSoftware Analysis	2013	18
Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation Ali Ahmadi, Ke Huang, Suriyaprakash Natarajan, Spatio-temporal Wafer-level CorrelationElectrical EngineeringInter-wafer Trend LearningEngineeringProbetest Measurements	2014	16
Selecting High-Quality Delay Tests for Manufacturing Test and Debug Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Proceedings EngineeringVerificationComputer ArchitectureReliability EngineeringComputational Testing	2006	14
Trouble-Shooting at GAN Point: Improving Functional Safety in Deep Learning Accelerators Shamik Kundu, Suvadeep Banerjee, Arnab Raha, IEEE Transactions on Computers	2023	11

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