A Comprehensive Model for Hot Carrier Degradation in LDMOS Transistors

Abstract

This paper presents a comprehensive yet physical model for hot carrier degradation in LDMOS transistors. The only model input parameters are the gate and drain voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs </sub> , the internal device temperature and the device width W. The model allows calculating AC degradation performance out of the DC hot carrier data. A physical explanation of the observed effects is provided, and important differences between LDMOS and standard CMOS are highlighted