IEEE Journal of Solid-State Circuits · 1990 · 70 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSystem-on-chip DesignCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingMixed-signal Integrated Circuit DesignTiming AnalysisAsynchronous Circuit DesignAsynchronous Digital Circuit DesignAsynchronous ProcessingClocked LogicFinite Impulse Response FiltersInfinite Impulse Response FiltersModular DesignSelf-testing Circuits
A complete, microprocessor-based, general-purpose digital signal processor (DSP) was designed and fabricated using self-timed circuits following a four-cycle handshake protocol to provide fully asynchronous operation without the need for any global clock. The methodology developed allows modular design, as has been traditionally performed in clocked systems. Versions of the DSP included an FIR (finite impulse response) filter, and IIR (infinite impulse response) filter, and a test program exercising all mathematical and control functionality. All operated correctly and showed cycle times comparable to clocked designs in the same technology. The DSP, designed in 2- mu m n-well CMOS, has an active area of 6.6 mm*4.7 mm, and instruction times range from 73 to 337 ns at 5 V, depending on the hardware requirements of each operation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Cascode voltage switch logic: A differential CMOS logic family
L.G. Heller, W. Paul Griffin, Jack Davis et al. · 1984 · 482 citations
Engineering, Computer Engineering, Electrical Engineering +14
The design of an asynchronous MIPS R3000 microprocessor
Alain J. Martin, Andrew Lines, Rajit Manohar et al. · 2002 · 325 citations
The design of an asynchronous microprocessor
Alain J. Martin, Steven M. Burns, T. K. Lee et al. · ACM SIGARCH Computer Architecture News · 1989 · 184 citations · Full text