International Symposium on Low Power Electronics and Design · 2011 · 13 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsCmos Circuit DesignConfigurable Logic BlocksDynamic Power ReductionIntegrated Circuit DesignLow-power Digital Circuit DesignPower OptimizationEnergy-efficient Digital CircuitsFlip-flopsLow-power Configurable Logic DesignLow-power Flip-flop DesignLow-power Logic DesignLow-voltage Cmos DesignOperating VoltagePower-efficient Logic Block Design
Contention-less flip-flops (CLFF's) and separated power supply voltages (V DD ) between flip-flops (FF's) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65-nm CMOS process. Measurement results of fabricated chips show that the proposed CLFF reduces the minimum operating voltage of IU's by 64mV on average. By scaling V DD from 1.2V to 310mV with the proposed CLFF, the maximum energy efficiency of 1835GOPS/W and the highest energy efficiency increase of 12.7 times are achieved.
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