Performance Comparison of Interconnect Technology and Architecture Options for Deep Submicron Technology Nodes

TLDR

Interconnect performance bottlenecks have prompted proposals such as on‑chip transmission lines, carbon‑nanotube, wafer‑level package, 3D, RF/microwave, and optical interconnects. The paper aims to accurately estimate the performance and power gains of these options and to understand the trade‑offs among key metrics. The study finds that 3D interconnects cut latency by 51 % and energy by 54 % at 45 nm, optical interconnects lower latency relative to scaled Cu/low‑k but offer no advantage over WLP, and CNT interconnects achieve a 42 % delay reduction versus scaled Cu/low‑k.

Abstract

Several technological and architectural solutions have been proposed to solve the "interconnect performance bottleneck", such as the use of on-chip transmission lines, carbon-nanotube (CNT) interconnects, wafer-level package (WLP) interconnects, 3D interconnects, RF and microwave interconnects and optical interconnects. It is essential to accurately estimate the interconnect performance and power gains achievable by these options and to understand the various trade-offs involved between the different metrics of interest. In this paper, an exhaustive comparison in terms of representative performance, energy and density metrics has been carried out among the different options for global interconnects. This analysis shows that 3D interconnects offer an attractive option to reduce the energy dissipation and propagation delay of long on-chip wires (51% and 54% reduction in latency and energy dissipation respectively at 45nm node). This analysis also shows that optical interconnects offer reduced latency compared to scaled Cu/low-k technologies but they do not offer significant improvement compared to other technologies like WLP interconnects (Beyne, 2003). It also follows from the analysis that CNT interconnects compare favorably to scaled Cu/low-k interconnects in terms of latency with a 42% reduction in delay