Buried layer/connecting layer high energy implantation for improved CMOS latch-up

Abstract

An integrated P-buried layer formed by MeV ion implantation combined with a localized P-connecting layer has been studied for latch-up isolation improvement for advanced CMOS technology. Latch-up trigger currents have been characterized with regards to buried layer dose/energy, connecting layer dose/energy, and n-well retrograde dose. Simulation results confirmed by data indicate that P/sup +/ injection trigger currents >450 /spl mu/A//spl mu/m can be achieved by utilizing certain combinations of B.L./C.L., and n-well retrograde doses for n+/p+ spacings=2.0 /spl mu/m. The B.L./C.L. process architecture shows great promise for providing an alternative isolation technique far latch-up improvement that is easy to implement, and for eliminating the dependence on epi silicon for latch-up control.