Understanding barrier engineered charge-trapping NAND flash devices with and without high-K dielectric

Abstract

Barrier engineered charge-trapping NAND flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multi-layer barrier is derived using WKB approximation. The rigorously derived analytical form is valid for both electron and hole tunneling, as well as for any barrier composition. With this, the time evolution (Vt-time) of any BE-CTNF device during programming/erasing can be accurately simulated. The model is validated by experimental results from bandgap-engineered SONOS (BE-SONOS) and various structures using Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> top-capping layer. Using this model, various structures of BE-CTNF with high-K tunneling or blocking dielectric are investigated. Furthermore, the low-field tunneling current for various structures are simulated, providing theoretical foundations for retention and read disturb optimization.