Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes

Abstract

Multiple bit upsets due to radiation-induced soft errors are a major concern in nanoscale technology nodes. Once such errors occur in the configuration frames of an FPGA device, they permanently affect the functionality of the mapped design. The combination of error correction schemes and configuration scrubbing is an efficient approach to avoid such permanent errors. Existing solutions exploit coding techniques with considerably high overhead to protect configuration frames against multiple bit upsets. In this paper, we propose a generic scrubbing scheme which reconstructs the erroneous configuration frame based on the concept of erasure codes. Our proposed scheme does not require any changes to the FPGA architecture. Experimental results on a Xilinx Virtex-6 FPGA device show that the proposed scheme achieves error recovery coverage of 99.30% with only 3% resource occupation while the mean time to repair is comparable with previous schemes.