Variability of flip-flop timing at sub-threshold voltages

Abstract

The design of sub-threshold circuits is especially challenging due to the massive impact of process variations. These variabilities also heavily affect circuit timing, a problem only considered concerning combinational gates so far. In this paper the effects of process variations on flip-flop timing at sub-threshold voltages are analyzed based on extensive monte-carlo simulations. The results show that the usual timing-optimal definition of timing parameters needs to be replaced by a reliability-driven approach. The model is validated for sub- and near-threshold supply voltages and an approach for energy-optimal sizing is presented.