N-channel depletion-mode InP FET with enhanced barrier height gates

Abstract

The fabrication of an n-channel depletion-mode InP field-effect transistor (FET) with enhanced barrier height gates, using a surface passivation technique that substantially increases the barrier height ( Phi /sub b/=0.83 eV) of InP, is reported. The transistors demonstrate characteristics with excellent pinch-off, flat saturation, transconductance in the range of 60-68 mS/mm, and no indication of the onset of breakdown for drain-source biases in excess of 35 V. They are shown to be highly stable, with no observable drain current drift over a period of more than 24 h of testing under DC bias. The high stability and performance of these devices demonstrate the potential for the gate metallization of InP.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>