IEEE Transactions on Circuits and Systems I Regular Papers · 2010 · 40 citations · 17 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureHardware Description LanguagesMicroelectronicsCmos Circuit DesignDelay ModelingDigital Integrated Circuit DesignDigital Logic DesignTiming AnalysisTiming ModelingCircuit Delay ModelingCmos Logic CircuitsCurrent-mode Circuit DesignCurrent-mode LogicGate Delay ModelingLogic GatesLow-noise DesignModel Accuracy Assessment
MOS current-mode logic (MCML) is a low-noise alternative to CMOS logic. The lack of MCML automation tools, however, has deterred designers from applying MCML to complex digital functions. This paper presents an efficient MCML optimization program that can be used to properly size MCML gates. The delay model accuracy is adjusted by fitting measured gate delays by means of technology-dependent parameters. For an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> number of logic gates, the proposed mathematical program has reduced the number of variables to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> +1, in comparison to 7 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> +1 in the most recent work on this topic. The program has been implemented to efficiently optimize a 4-bit ripple carry adder and an 8-bit decoder in 0.18-μm CMOS technology.
17