Intermittency detection and mitigation in Ball Grid Array (BGA) packages

Abstract

An update on a method (SJ BIST™) to detect intermittencies in Ball Grid Array (BGA) packages is presented, and another method (SJ Monitor™) is introduced. SJ BIST™ is primarily firmware embedded in the FPGA application; SJ Monitor™ is hardware on an IC chip. Failure of monitored I/O pins on operational, fully-programmed FPGAs is reported by SJ BIST and SJ Monitor to provide positive indication of damage to one or more I/O solder-joint networks of an FPGA on an electronic digital board. The board can then be replaced before accumulated fatigue damage results in intermittent or long-lasting operational faults.