MVL circuit design and characterization at the transistor level using SUS-LOC

Abstract

This paper deals with design and performance estimation of typical ternary functions using SUS-LOC concepts. Experimental models of the transistors needed for SUS-LOC structures are presented. A created characterization process allows to extract the delay and the energy consumption information from each cell which is simulated at the transistor level. Finally, VHDL is used to obtain performances modelling and architectural-level simulation. Some characterization results are presented for basic logic ternary functions and a comparison between binary and ternary circuits is given for two adder structures.