Application of RHBD Techniques to SEU Hardening of Third-Generation SiGe HBT Logic Circuits

Abstract

Shift registers featuring radiation-hardening-by-design (RHBD) techniques are realized in IBM 8HP SiGe BiCMOS technology. Both circuit and device-level RHBD techniques are employed to improve the overall SEU immunity of the shift registers. Circuit-level RHBD techniques include dual-interleaving and gated-feedback that achieve SEU mitigation through local latch-level redundancy and correction. In addition, register-level RHBD based on triple-module redundancy (TMR) versions of dual-interleaved and gated-feedback cell shift registers is also realized to gauge the performance improvement offered by TMR. At the device-level, RHBD C-B-E SiGe HBTs with single collector and base contacts and significantly smaller deep trench-enclosed area than standard C-B-E-B-C devices with dual collector and base contacts are used to reduce the upset sensitive area. The SEU performance of these shift registers was then tested using heavy ions and standard bit-error testing methods. The results obtained are compared to the unhardened standard shift register designed with CBEBC SiGe HBTs. The RHBD-enhanced shift registers perform significantly better than the unhardened circuit, with the TMR technique proving very effective in achieving significant SEU immunity