Low-resistance self-aligned Ti-silicide technology for sub-quarter micron CMOS devices

Abstract

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-/spl mu/m CMOS devices with low-resistance and uniform TiSi/sub 2/ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi/sub 2/ films were achieved on all narrow, long n/sup +/ and p/sup +/ poly-Si and diffusion layers of 0.15-/spl mu/m CMOS devices. TiSi/sub 2/ films with a sheet resistance of 5 to 7 /spl Omega//sq were stably and uniformly formed on 0.15-/spl mu/m-wide n/sup +/ and p/sup +/ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi/sub 2/ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-/spl mu/m NMOSFET's and PMOSFET's with self-aligned TiSi/sub 2/ films.