2002 · 36 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsClock GatingClock ManagementDigital Logic DesignLow-power Digital Circuit DesignTiming AnalysisTiming ModelingClock Gating For Digital CircuitsClock GenerationClock Power DissipationDynamic Power DissipationFlip-flopsLow-power Cmos DesignLow-power Flip-flop DesignSequential Clock Gating
The paper models sequential circuit clock behavior with a quaternary variable to propose and analyze two clock‑gating techniques. The authors generate derived clocks per flip‑flop using the covering relationship between clock transitions and flip‑flop active cycles, and present a synchronous derived‑clock technique with design examples. Experiments demonstrate that the gated‑clock designs preserve logic functionality while reducing power dissipation relative to conventional designs.
This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock-gating techniques. It then uses the covering relationship between the triggering transition of the clock and the active cycles of various flip flops to generate a derived clock for each flip flop in the circuit. A technique for clock gating is also presented, which generates a derived clock synchronous with the master clock. Design examples using gated clocks are provided next. Experimental results show that these designs have ideal logic functionality with lower power dissipation compared to traditional designs.
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