Clock Power Dissipation
Clock Power Dissipation is the static and dynamic power consumption attributable to the generation, distribution, and switching of clock signals within a synchronous digital circuit, distinguished from other forms of power dissipation by its direct dependence on clock network activity and capacitance.
193
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6.9K
Citations
667
Authors
190
Institutions
Publications per year
2017–2026
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University of Michigan
Ann Arbor, United States
7 h-index
18 publications
592 citations

Chitkara University
Chandigarh, India
5 h-index
21 publications
332 citations
University of Southern California
Los Angeles, United States
5 h-index
8 publications
718 citations

University of Notre Dame
Notre Dame, United States
5 h-index
30 publications
1.6K citations
Texas A&M University
College Station, United States
5 h-index
11 publications
343 citations
South Asian University
New Delhi, India
4 h-index
21 publications
343 citations

National Taiwan University
Taipei, Taiwan
4 h-index
9 publications
469 citations
Panasonic (Japan)
Kadoma, Japan
4 h-index
38 publications
881 citations
1–8 of 190
24 publications · 1.4K citations
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9 publications · 346 citations
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7 publications · 154 citations
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5 publications · 147 citations
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4 publications · 169 citations
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