Clock Power Dissipation

Clock Power Dissipation is the static and dynamic power consumption attributable to the generation, distribution, and switching of clock signals within a synchronous digital circuit, distinguished from other forms of power dissipation by its direct dependence on clock network activity and capacitance.

193

Publications

6.9K

Citations

667

Authors

190

Institutions

Publications per year

2017–2026

24

Authors

667

  1. BP
    Bishwajeet Pandey

    Chitkara University, India

    12 publications · 241 citations

    11

    h-index

  2. GH
    Gary H. Bernstein

    University of Notre Dame, United States

    4 publications · 218 citations

    4

    h-index

  3. TD
    Teerath Das

    South Asian University, India

    4 publications · 64 citations

    4

    h-index

  4. TK
    Tanesh Kumar

    University of Oulu, Finland

    4 publications · 64 citations

    4

    h-index

  5. MP
    Massoud Pedram

    University of Southern California, United States

    4 publications · 336 citations

    4

    h-index

1–5 of 667

Venues

  1. IEEE Journal of Solid-State Circuits

    24 publications · 1.4K citations

    21

    h-index

  2. 9

    h-index

  3. IEEE Transactions on Applied Superconductivity

    7 publications · 154 citations

    7

    h-index

  4. 5

    h-index

  5. 4

    h-index

1–5