Concepedia

B. Pouya

BP

8

Publications

571

Citations

8

H-Index

1997

Active since

Affiliations

The University of Texas at Austin(Current)

Motorola (United States)

B. Pouya is an author at The University of Texas at Austin specializing in hardware security, design for testing, and computer engineering.

Top concepts

EngineeringSoftware TestingHardware SecurityDesign For TestingComputer EngineeringComputer ArchitectureComputer ScienceParallel ComputingBuilt-in Self-testProgram Analysis

Publications per year

1997–2004

8

Publications

8

Reducing power dissipation during test using scan chain disable

Rajkumar Sankaralingam, B. Pouya, Nur A. Touba · 2002 · 149 citations

Full Scan Module, Engineering, Power Optimization (Eda) +16

Virtual scan chains: a means for reducing scan length in cores

Abhijit Jas, B. Pouya, Nur A. Touba · 2002 · 93 citations

Engineering, Computer Architecture, Scan Length +22

Testing embedded cores using partial isolation rings

Nur A. Touba, B. Pouya · 2002 · 92 citations

Partial Isolation, Engineering, Hardware Verification Language +18

Synthesis of zero-aliasing elementary-tree space compactors

B. Pouya, Nur A. Touba · 2002 · 76 citations

Engineering, Vlsi Design, Mem Testing +16

Optimization trade-offs for vector volume and test power

B. Pouya, Alfred L. Crouch · 2002 · 57 citations

Numerical Analysis, Large-scale Global Optimization, Engineering +20

Rows per page

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