Concepedia

Sequential Clock Gating

Sequential Clock Gating is a clock gating methodology that selectively disables the clock signal to sequential elements in a digital circuit based on activity detection in preceding computation stages to reduce dynamic power consumption.

9

Publications

571

Citations

25

Authors

11

Institutions

Publications per year

2017–2026

0

Parents

Publications

9

Clock-gating and its application to low power design of sequential circuits

Qing Wu, Massoud Pedram, Xunwei Wu · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 2000 · 254 citations

, , +17

Saving power by synthesizing gated clocks for sequential circuits

Luca Benini, Paul H. Siegel, Giovanni De Micheli · IEEE Design & Test of Computers · 1994 · 170 citations

, , +17

Clock-gating and its application to low power design of sequential circuits

Qing Wu, Massoud Pedram · 2002 · 36 citations

, , +17

Clock gated low power sequential circuit design

Mahendra Pratap Dev, Deepak Baghel, Bishwajeet Pandey et al. · 2013 · 35 citations

, , +17

Low power sequential circuit design by using priority encoding and clock gating

Xunwei Wu, Massoud Pedram · 2000 · 19 citations

, , +16

1–5 of 9

Authors

25

  1. MP
    Massoud Pedram

    University of Southern California, United States

    3 publications · 309 citations

    3

    h-index

  2. SA
    Sumit Ahuja

    Virginia Tech, United States

    1 publications · 13 citations

    1

    h-index

  3. LL
    Li Li

    University of Technology Sydney, Australia

    1 publications · 12 citations

    1

    h-index

  4. MP
    Manisha Pattanaik

    Atal Bihari Vajpayee Indian Institute of Information Technology and Management, India

    1 publications · 35 citations

    1

    h-index

  5. WW
    Wei Wang

    Chinese Academy of Sciences, China

    1 publications · 12 citations

    1

    h-index

1–5 of 25

Institutions

11

  1. University of Southern California

    Los Angeles, United States

    3 h-index

    5 publications

    599 citations

  2. Engineering Systems (United States)

    Omaha, United States

    2 h-index

    4 publications

    580 citations

  3. Ningbo University

    Ningbo, China

    2 h-index

    2 publications

    273 citations

  4. University of California, Berkeley

    Berkeley, United States

    1 h-index

    2 publications

    28 citations

  5. Mentor Technologies

    Tulsa, United States

    1 h-index

    1 publications

    18 citations

  6. Atal Bihari Vajpayee Indian Institute of Information Technology and Management

    Gwalior, India

    1 h-index

    5 publications

    175 citations

  7. Illinois Institute of Technology

    Chicago, United States

    1 h-index

    3 publications

    36 citations

  8. Hewlett-Packard (Japan)

    Tokyo, Japan

    1 h-index

    1 publications

    170 citations

1–8 of 11

Venues

  1. IEEE Design & Test of Computers

    1 publications · 170 citations

    1

    h-index

  2. 1

    h-index

1–2