IEEE Journal of Solid-State Circuits · 2007 · 45 citations · 21 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsClock GatingLeakage Power ReductionLow-power Digital Circuit DesignPower GatingPower ManagementPower OptimizationArea Overhead AnalysisCurrentsFine-grained Power GatingFine-grained Power ManagementLeakageLeakage Power OptimizationPower DistributionPower-aware Hardware Architecture
Hierarchical power distribution with a power tree has been developed. The key features are a power-tree structure with three power-tree management rules and a distributed common power domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1 000 000-gate power domain were effectively reduced to 1/4000 in multi-CPU SoCs with minimal area overhead
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Low-power embedded SRAM modules with expanded margins for writing
Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki et al. · 2005 · 136 citations
Engineering, Computer Engineering, Electrical Engineering +17
90nm low leakage SoC design techniques for wireless applications
Philippe Royannez, H. Mair, Franck Dahan et al. · 2005 · 100 citations
Engineering, Computer Engineering, Electrical Engineering +17