Yoshihiko Yasu - Concepedia

Author

Yoshihiko Yasu

Hitachi (Japan)

Also Known As

Y. Yasu, Yoshihiko Yasu

Publications

299

Citations

H-Index

Concepts

All Affiliations

Hitachi (Japan)Renesas Electronics (Japan)Renesas Electronics (United States)

About

Yoshihiko Yasu is an author at Hitachi (Japan) specializing in engineering, computer engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	270
2	Computer Engineering	9	9	270
3	Electrical Engineering	6	6	163
4	Education	2	2	40
5	Computer Science	2	2	85

Yoshihiko Yasu

Publications

270

Citations

H-Index

Page 1

	Year	Citations
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, EngineeringVlsi DesignPower Optimization (Eda)Computer ArchitecturePower Electronics	2006	50
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, IEEE Journal of Solid-State Circuits EngineeringPower Optimization (Eda)Computer ArchitecturePower ElectronicsPower Domains	2007	45
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler Masayuki Itô, Toshihiro Hattori, Yutaka Yoshida, EngineeringComputer ArchitectureIndependent Power-off ControlEmbedded ApplicationsPower Optimization	2008	43
A resume-standby application processor for 3G cellular phones T. Kamei, Masatoshi Ishikawa, T. Hiraoka, EngineeringVlsi DesignComputer ArchitectureProcessor ArchitectureMulti-channel Memory Architecture	2004	42
In-Situ Measurement of Supply-Noise Maps with Millivolt Accuracy and Nanosecond-Order Time Resolution Yusuke Kanno, Yuki Kondoh, Takahiro Irita, Supply-noise MapsPrecision MeasurementEngineeringMeasurementCalibration	2006	22
A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current Kazuhiro Sato, K. Kenmizaki, S. Kubono, IEEE Journal of Solid-State Circuits Non-volatile MemoryEngineeringEmerging Memory TechnologyPsram OperationComputer Architecture	1991	19
In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution Yusuke Kanno, Yuki Kondoh, Takahiro Irita, IEEE Journal of Solid-State Circuits EngineeringMeasurementAnalog DesignEducationNanosecond-order Time Resolution	2007	18
Hierarchical power distribution and power management scheme for a single chip mobile processor Toshihiro Hattori, Takao Koike, Yoshihiko Tsuchihashi, EngineeringEnergy EfficiencyPower Optimization (Eda)Computer ArchitecturePower Electronics	2006	16
μI/O architecture for 0.13-μm wide-voltage-range system-on-a-package (SoP) designs Yusuke Kanno, Hiroyuki Mizuno, N. Oodaira, Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignMulti-chip Package	2003	15

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