IEEE Transactions on Electron Devices · 1992 · 37 citations · 9 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsDevice ModelingIon ImplantationMetal-oxide-semiconductor Field-effect TransistorsNanoelectronicsSemiconductor InterfacesSilicon MaterialsAmorphous SiliconBoron IncorporationGate Oxide InterfacesGate OxidesInterface DensitySiliconThreshold VoltageThreshold Voltage Modeling
Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V/sub TP/) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V/sub TP/ shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO/sub 2//Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V/sub TP/ shift.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Hot-electron hardened Si-gate MOSFET utilizing F implantation
Yasushiro Nishioka, K. Ohyu, Yuzuru Ohji et al. · IEEE Electron Device Letters · 1989 · 104 citations