Nanoscale CMOS at low temperature: design, reliability, and scaling trend

Abstract

The semiconductor industry is not motivated to make practical use of cryogenic operation as long as IC performance could be improved at room temperature. However, as CMOS approaches the scaling limits, cooled chip operation becomes an attractive alternative. This paper explores the feasibility of IC temperature "scaling" and its implications to device performance and reliability for sub-50 nm CMOS generations.