Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

TLDR

Power limits on a single die constrain next‑generation CMP performance, but photonic interconnects promise higher bandwidth, lower latency, and significantly reduced power dissipation, making on‑chip photonic communication a feasible opportunity despite remaining challenges. The authors propose photonic networks‑on‑chip to mitigate intra‑ and off‑chip communication power, introducing a hybrid micro‑architecture that couples a broadband photonic circuit‑switched network with an electronic packet‑switched control overlay. They address key design issues—topology, routing, deadlock avoidance, and path‑setup/tear‑down—using the POINTS event‑driven simulator to compare the power of the photonic NoC against a conventional electronic NoC. Experimental results confirm that integrating optics via photonic NoCs delivers unique benefits for future CMPs, achieving lower overall power consumption while maintaining high bandwidth and low latency.

Abstract

The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intra-chip and off-chip communication on the overall power budget. A photonic interconnection network can deliver higher bandwidth and lower latencies with significantly lower power dissipation. We explain why on-chip photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize its implementation. We introduce a novel hybrid micro-architecture for NoCs combining a broadband photonic circuit-switched network with an electronic overlay packet-switched control network. We address the critical design issues including: topology, routing algorithms, deadlock avoidance, and path-setup/tear-down procedures. We present experimental results obtained with POINTS, an event-driven simulator specifically developed to analyze the proposed idea, as well as a comparative power analysis of a photonic versus an electronic NoC. Overall, these results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs.