High-speed, high-bandwidth DRAM memory bus with crosstalk transfer logic (XTL) interface

Abstract

Crosstalk Transfer Logic (XTL) is a digital-signal interface that uses directional couplers to form parallel lines within a circuit board. An advantage of the XTL is that it provides a multi-drop and high-speed system that is a one-to-many connection that can be used as a memory bus. To evaluate the signal integrity of an XTL to be applied to a DRAM bus, a test chip and boards were developed. We describe the design of the bus and report the results of its evaluation in this paper. The test chip was designed using a 0.15-/spl mu/m CMOS process and it had a controllable offset of the hysteresis receiver. A folding coupler was applied to the motherboard to condense the wiring and to reduce the noise from adjacent signals. The mother-board had only two coupler layers, with a four-byte data width, and it was capable of having eight modules mounted on the bits. The experimental results showed that the WRITE and READ operation reached speeds of at least 500 Mbps when eight modules were mounted on the bus.