IEEE Transactions on Nuclear Science · 2008 · 64 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesCharge Carrier TransportDevice CharacterizationDevice ModelingDevice SimulationElectric CircuitsIntegrated Circuit DesignCharge CollectionCharge Collection ElectronicsCharge ExtractionCharge TrappingCharge TrapsGate Charge ManagementPulse Width Optimization
3D-TCAD simulations in a 130-nm process are used to show the effect of guard rings and guard drains in mitigating charge collection and charge sharing between nodes. Experimental results quantifying the reduction in SET pulse width and the error cross section were obtained with the use of SET pulse width and SET error rate measurement test circuits fabricated in 130-nm and 180-nm processes. Results indicate that guard drains results in 30% lower error cross section compared to guard ring circuits.
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Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices
N. Seifert, P. Slankard, Martin Kirsch et al. · 2006 · 203 citations
Engineering, Computer Engineering, Electrical Engineering +17