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Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface
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2003
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Low-power ElectronicsElectrical Engineering70-Nm Technology NodeEngineeringOxygen-enriched InterfaceNanoelectronicsElectronic EngineeringBias Temperature InstabilityApplied PhysicsHigh-k Offset SpacerHigh-epsilon Offset SpacerFemto-second Cmos TechnologySilicon On InsulatorMicroelectronicsSemiconductor Device40-Nm Cmos Transistors
We demonstrate 40-nm CMOS transistors for the 70-nm technology node. This transistor uses a high-k offset spacer (EOS: high-epsilon offset spacer) in achieving both a short-channel and high drivability along with SiN gate dielectrics with oxygen-enriched interface (OI-SiN) to suppress both the gate-leakage current and boron penetration. Consequently, N-MOSFET and P-MOSFET have high drive currents of 0.68 and 0.30 mA//spl mu/m, respectively, with I/sub off/=10 nA//spl mu/m, with an EOT value of 1.4 nm. The record gate delay of 280 fs (3.6 THz), for an N-MOSFET with the gate length of 19 nm, has also been achieved.