K. Ohnishi

Negative bias temperature instability of pMOSFETs with ultra-thin SiON gate dielectrics

Shigeo Tsujikawa, Toshiyuki Mine, Kenji Watanabe et al. · 2003 · 75 citations

Electrical Engineering, Engineering, Physics +10

Experimental evidence for the generation of bulk traps by negative bias temperature stress and their impact on the integrity of direct-tunneling gate dielectrics

Shigeo Tsujikawa, Kenji Watanabe, Ryuta Tsuchiya et al. · 2004 · 31 citations

Positive Bias Stress, Electrical Engineering, Semiconductor Device +15

EXTRINSIC SYMPATHETIC REINNERVATION AFTER INTESTINAL TRANSPLANTATION IN RATS

Hidenori Kiyochi, ATSUMI ONO, Naritaka Yamamoto et al. · Transplantation · 1995 · 29 citations

Regenerative Medicine, Transplantation Surgery, Extrinsic Reinnervation +13

Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface

Ryuta Tsuchiya, K. Ohnishi, M. Horiuchi et al. · 2003 · 15 citations

Low-power Electronics, Electrical Engineering, 70-Nm Technology Node +13

A raised source/drain technology using in-situ P-doped SiGe and B-doped Si for 0.1-μm CMOS ULSIs

T. Uchino, T. Shiba, K. Ohnishi et al. · 2002 · 13 citations

Electrical Engineering, Engineering, In-situ P-doped Sige +11