2011 · 117 citations · 15 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureInterconnection NetworksLow-power DesignCluster ArchitectureInterconnect ArchitectureInterconnect DesignInterconnect FabricsPhysical DesignRoutingArea-delay OptimizationDesign ConstraintsInterconnect Delay OptimizationInterconnect Network DesignInterconnect OptimizationInterconnect Power OptimizationInterconnection Network SynthesisPhysical Design Automation
Shared L1 memory is a promising architectural option for tightly‑coupled multi‑core processor clusters. The authors designed a parametric, fully combinational Mesh‑of‑Trees interconnection network to enable high‑performance, single‑cycle communication between processors and memories in L1‑coupled clusters. The interconnect IP is implemented in synthesizable RTL and optimized through a design‑automation strategy that blends advanced synthesis and physical optimization to achieve optimal delay, power, and area across many configurations in 65 nm technology. Post‑placement and routing, the 8×16 configuration achieves a 38 FO4 delay, which grows almost logarithmically to 84 FO4 when both processors and memories are quadrupled, and the design offers a 45 % power and 12 % area savings at only a 30 % performance loss compared to the max‑performance 16×32 configuration.
Shared L1 memory is an interesting architectural option for building tightly-coupled multi-core processor clusters. We designed a parametric, fully combinational Mesh-of-Trees (MoT) interconnection network to support high-performance, single-cycle communication between processors and memories in L1-coupled processor clusters. Our interconnect IP is described in synthesizable RTL and it is coupled with a design automation strategy mixing advanced synthesis and physical optimization to achieve optimal delay, power, area (DPA) under a wide range of design constraints. We explore DPA for a large set of network configurations in 65nm technology. Post placement&routing delay is 38FO4 for a configuration with 8 processors and 16 32-bit memories (8×16); when the number of both processors and memories is increased by a factor of 4, the delay increases almost logarithmically, to 84FO4, confirming scalability across a significant range of configurations. DPA tradeoff flexibility is also promising: in comparison to the maxperformance 16×32 configuration, there is potential to save power and area by 45% and 12 % respectively, at the expense of 30% performance degradation.
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