1990 · 136 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsOptimizationCmos Circuit DesignDelay ModelingLow-power Digital Circuit DesignPower OptimizationPower-aware DesignTiming AnalysisCircuit Delay ModelingDelay OptimizationDigital Circuit OptimizationGate Delay ModelingGate SizingPower ConsumptionPower Consumption ModelingPower Consumption Optimization
In this paper a solution is presented to tune the delay of a circuit composed of cells to a prescribed value, while minimizing power consumption. The tuning is performed by adapting the load drive capabilities of the cells. This optimization problem is mapped onto a linear program, which is then solved by the Simplex algorithm. This approach guarantees to find the global optimum, and has proven feasible for circuits of up to several thousand cells. The method can be used with any convex delay model. Results show that circuits can be speeded up by a factor of 2 at a cost of only 10 to 30% of extra power.
6
Optimization-based transistor sizing
J.-M. Shyu, Alberto Sangiovanni‐Vincentelli, J.P. Fishburn et al. · IEEE Journal of Solid-State Circuits · 1988 · 179 citations
Timing optimization of combinational logic
K.J. Singh, A.R. Wang, Robert K. Brayton et al. · 2003 · 173 citations
Transistor size optimization in the tailor layout system
David Marple · 1989 · 79 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17